/*!
    \file    change log.txt
    \brief   change log for GD32A508 firmware

    \version 2026-02-09 V1.4.0, firmware for GD32A508
*/

/*
    Copyright (c) 2024, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

******************* V1.4.0 2026-02-09 ******************************************************************************************
______________________Common______________________________________________________________________________________________


______________________________________________________________________________________________________________________________

______________________PMU____________________________________________________________________________________________

Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/PMU/Deepsleep_wakeup_RTC/main.c
/fw3233/GD32A508_Firmware_Library/Examples/PMU/Deepsleep_wakeup_exti/main.c
/fw3233/GD32A508_Firmware_Library/Examples/PMU/Standby_wakeup_RTC/main.c
/fw3233/GD32A508_Firmware_Library/Examples/PMU/Standby_wakeup_pin/main.c
fix reason:
切频补丁添加
V1.3.0:
NONE
V1.4.0:
/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}

__________________________________________________________________________________________________________________________

______________________USB____________________________________________________________________________________________

Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/USBHS/usb_device/dev_firmware_update/src/inter_flash_if.c
fix reason:
Programming and erasing add flag bit clearing instructions


V1.3.0:
static uint8_t flash_if_erase(uint32_t addr)
{
    /* unlock the internal flash */
    fmc_unlock();

    fmc_page_erase(addr);

    /* lock the internal flash */
    fmc_lock();

    return MEM_OK;
}
V1.4.0:
static uint8_t flash_if_erase(uint32_t addr)
{
    /* unlock the internal flash */
    fmc_unlock();

    /* clear all pending flags */
    fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGAERR | FMC_FLAG_PGERR);

    fmc_page_erase(addr);

    /* lock the internal flash */
    fmc_lock();

    return MEM_OK;
}

	
 Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_usbhs_library/device/class/iap/Include/usb_iap_core.h
fix reason:
Add 4-byte alignment to the variable


V1.3.0:
typedef struct {
    uint8_t report_buf[IAP_OUT_PACKET];                                            /*!< report buff */
    uint8_t option_byte[IAP_IN_PACKET];                                            /*!< option byte buff */

    /* state machine variables */
    uint8_t dev_status[IAP_IN_PACKET];                                             /*!< device status */
    uint8_t bin_addr[IAP_IN_PACKET]; 
V1.4.0:
typedef struct {
    __ALIGN_BEGIN uint8_t report_buf[IAP_OUT_PACKET] __ALIGN_END;                  /*!< report buff */
    __ALIGN_BEGIN uint8_t option_byte[IAP_IN_PACKET] __ALIGN_END;                  /*!< option byte buff */

    /* state machine variables */
    __ALIGN_BEGIN uint8_t dev_status[IAP_IN_PACKET] __ALIGN_END;                   /*!< device status */
    __ALIGN_BEGIN uint8_t bin_addr[IAP_IN_PACKET] __ALIGN_END;        
none
	
	
 Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/USBHS/usb_device/composite_dev_hid_printer/MDK-ARM/composite_hid_printer.uvprojx
fix reason:
Modify the name of the compiled output

V1.3.0:

V1.4.0:

 Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/USBHS/usb_device/in_application_program_hid/inc/usbd_conf.h
/fw3233/GD32A508_Firmware_Library/Examples/USBHS/usb_device/in_application_program_hid/src/flash_operation.c
fix reason:
Fix the issue of write failure in the flash area


V1.3.0:

V1.4.0:


__________________________________________________________________________________________________________________________

______________________CAN____________________________________________________________________________________________

Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Include/gd32a508_can.h
fix reason:
Fixed the CAN filter register's address bug

V1.3.0:
#define CAN_F23DATA0(canx)                 REG32((canx) + 0x000003F8U)
V1.4.0:
#define CAN_F23DATA0(canx)                 REG32((canx) + 0x000002F8U) 
 
__________________________________________________________________________________________________________________________

______________________I2S____________________________________________________________________________________________

Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Include/gd32a508_spi.h
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Source/gd32a508_spi.c
fix reason:
I2S phillips 改为 philips

V1.3.0:

V1.4.0:

__________________________________________________________________________________________________________________________

______________________DMA_______________________________________________________________________________________________
Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/DMA/Ram_to_usart/gd32a508_it.c
/fw3233/GD32A508_Firmware_Library/Examples/DMA/Ram_to_usart/gd32a508_it.h
fix reason: 
The missing DMA of the it.c file completes the interrupt handling interface,Add DMA to the it.c file to complete the interrupt handling interface

V1.3.0:
NONE

V1.4.0:
void PendSV_Handler(void)
{
    /* if PendSV exception occurs, go to infinite loop */
    while(1) {
    }
}

/*!
    \brief      this function handles DMA0_Channel3_IRQHandler interrupt
    \param[in]  none
    \param[out] none
    \retval     none
*/
void DMA0_Channel3_IRQHandler(void)
{
    if(dma_interrupt_flag_get(DMA0, DMA_CH3, DMA_INT_FLAG_FTF)){
        dma_interrupt_flag_clear(DMA0, DMA_CH3, DMA_INT_FLAG_G);
        g_transfer_complete = SET;
    }
}
___________________________________________________________________________________________________________

______________________BKP______________________________________________________________________________________________
Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/BKP/Backup_data/main.c
/fw3233/GD32A508_Firmware_Library/Examples/BKP/Tamper/main.c
fix reason: 
若RCU_BDCTL_BKPRST位置位时读BKP_DATAx，会导致MCU宕机/跑飞。需要在访问备份域内容之前先判断RCU_BDCTL_BKPRST位是否已清零，若置位则清除。
在访问备份域内容之前先判断RCU_BDCTL_BKPRST位是否已清零，若置位则清除


V1.3.0:
NONE

V1.4.0:
int main(void)
{
    /* led configuration and turn on all led */
    led_config();
    /* PMU lock enable */
    rcu_periph_clock_enable(RCU_PMU);
    /* BKP clock enable */
    rcu_periph_clock_enable(RCU_BKPI);
    /* enable write access to the registers in backup domain */
    pmu_backup_write_enable();
    /* confirm RCU_BDCTL_BKPRST bit is reset */
    if(RESET != (RCU_BDCTL & RCU_BDCTL_BKPRST)){
        rcu_bkp_reset_disable();
    }
___________________________________________________________________________________________________________

______________________RCU______________________________________________________________________________________________
Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/CMSIS/GD/GD32A508/Source/system_gd32a508.c
fix reason: 
Delete  __SYS_OSC_CLK macro define



V1.3.0:


V1.4.0:

Fix file:
/fw3233/GD32E50x_Firmware_Library/Firmware/GD32E50x_standard_peripheral/Include/gd32e50x_rcu.h
/fw3233/GD32E50x_Firmware_Library/Firmware/GD32E50x_standard_peripheral/Source/gd32e50x_rcu.c

fix reason: 
HD add PLLSCTL register. add rcu_spread_spectrum_config/rcu_spread_spectrum_enable/rcu_spread_spectrum_disable function




V1.3.0:
oid rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
{
    uint32_t reg;
    
    reg = RCU_CTL;
    /* reset the IRC8MADJ bits and set according to irc8m_adjval */
    reg &= ~RCU_CTL_IRC8MADJ;
    RCU_CTL = (reg | ((irc8m_adjval & RCU_IRC8M_ADJUST_MASK) << RCU_IRC8M_ADJUST_OFFSET));
}

/*!

V1.4.0:
void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
{
    uint32_t reg;
    
    reg = RCU_CTL;
    /* reset the IRC8MADJ bits and set according to irc8m_adjval */
    reg &= ~RCU_CTL_IRC8MADJ;
    RCU_CTL = (reg | ((irc8m_adjval & RCU_IRC8M_ADJUST_MASK) << RCU_IRC8M_ADJUST_OFFSET));
}

/*!
    \brief    configure the spread spectrum modulation for the main PLL clock
    \param[in]  spread_spectrum_type: PLL spread spectrum modulation type select
      \arg        RCU_SS_TYPE_CENTER: center spread type is selected
      \arg        RCU_SS_TYPE_DOWN: down spread type is selected
    \param[in]  modstep: configure PLL spread spectrum modulation profile amplitude and frequency
      \arg        This parameter should be selected between 0 and 7FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1
    \param[in]  modcnt: configure PLL spread spectrum modulation profile amplitude and frequency
      \arg        This parameter should be selected between 0 and 1FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1
    \param[out] none
    \retval     none
*/
void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt)
{
    uint32_t reg;

    reg = RCU_PLLSSCTL;
    /* reset the RCU_PLLSSCTL register bits */
    reg &= ~(RCU_PLLSSCTL_MODCNT | RCU_PLLSSCTL_MODSTEP | RCU_PLLSSCTL_SS_TYPE);
    RCU_PLLSSCTL = (reg | spread_spectrum_type | modstep << 13 | modcnt);
}

/*!
    \brief    enable the PLL spread spectrum modulation
    \param[in]  none
    \param[out] none
    \retval     none
*/
void rcu_spread_spectrum_enable(void)
{
    RCU_PLLSSCTL |= RCU_PLLSSCTL_SSCGON;
}

/*!
    \brief    disable the PLL spread spectrum modulation
    \param[in]  none
    \param[out] none
    \retval     none
*/
void rcu_spread_spectrum_disable(void)
{
    RCU_PLLSSCTL &= ~RCU_PLLSSCTL_SSCGON;
}

___________________________________________________________________________________________________________

______________________FMC______________________________________________________________________________________________
Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/FMC/Erase_program/main.c
/fw3233/GD32A508_Firmware_Library/Examples/FMC/Security_protection/main.c
/fw3233/GD32A508_Firmware_Library/Examples/FMC/Write_protection/main.c
fix reason: 
Clear the flag before operation to prevent the flag from being set due to other operations inserted by the customer, which may affect the next operation.
Modifying Content:Before operating (erasing/writing) flash and option bytes, add the operation to clear all flags.




V1.3.0:
void fmc_program(void)
{
    /* unlock the flash program/erase controller */
    fmc_unlock();

    address = FMC_WRITE_START_ADDR;


V1.4.0:
void fmc_program(void)
{
    /* unlock the flash program/erase controller */
    fmc_unlock();
    /* clear all pending flags */
    fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGAERR | FMC_FLAG_PGERR);
    
    address = FMC_WRITE_START_ADDR;



___________________________________________________________________________________________________________






